FIG. 9(a) is a top view of a unit pixel section of a conventional MOS solid-state imaging device (an amplification type image sensor). FIG. 9(b) is a cross-sectional view of FIG. 9(a) along an A-A′ line. In a well 105, which is formed by adding a P-type impurity to a surface of a semiconductor substrate 110, a photoelectric converter section 102, a hole storage layer 103 and a drain region 104 are formed. A conductivity type of the photoelectric converter section 102 and the drain region 104 is an N-type, and the conductivity type of the hole storage layer 103 is a P-type. The photoelectric converter section 102 forms a PN junction with the well 105, thereby constituting a photodiode. An element isolating region 111 is formed around a region including the photoelectric converter section 102 and the drain region 104. A gate electrode 106 is situated above a surface of the well 105 having an insulating film 109 sandwiched therebetween.
The photoelectric converter section 102, the drain region 104, and the gate electrode 106 respectively correspond to a source, a drain and a gate of the MOS transistor, and thus this type of solid-state imaging device is called a MOS solid-state imaging device. Light condensed by a microlens, which is not shown, is incident on the photoelectric converter section 102, and a signal charge (free electrons) corresponding to an amount of the incident light is accumulated thereon. The hole storage layer 103 is provided so as to reduce a dark output.
A plurality of the unit pixel sections, each including an amplifying transistor which amplifies an output of the drain region 104, a reset transistor which discharges a signal charge of the drain region 104 and the like, is situated in a photoreceptor region of a chip in a matrix format. In a peripheral circuit region, which is a peripheral region of the photoreceptor region, a vertical scanning circuit and a horizontal scanning circuit are situated so as to drive each of the unit pixel sections. As shown in FIG. 10, which is a schematic cross-sectional view of the solid-state imaging device, to the well 105 in a photoreceptor region 130 and a peripheral circuit region 140, a reference voltage Vss (a ground voltage) is supplied constantly through reference voltage wiring 112.
When a gate voltage is applied to the gate electrode 106 of a transistor 101, a channel is formed in the surface of the well 105, and the signal charge accumulated in the photoelectric converter section 102 is transferred to the drain region 104. The drain region 104 temporarily accumulates the signal charge, and outputs a voltage signal corresponding to an amount of the signal charge.
FIG. 9(c) shows a potential of the surface of the well 105 in a stationary state. The stationary state is a state where no voltage is applied to the gate electrode 106. In the stationary state, a potential of the well 105 of a P-conductivity type is low, and a potential of the photoelectric converter section 102 and the drain region 104, which are each of a N-conductivity type, is high, and a potential changes gradually at a PN junction portion. Since a surface defect is generated in the surface of the well 105 due to a stress at the time of forming the insulating film 109, there are many free electrons in this area. In the stationary state, a region having the surface defect is covered by a depletion layer which is generated at a junction between the well 105 and the photoelectric converter section 102, and also by a depletion layer which is generated at a portion of the surface of the well 105 under the gate electrode 106, and thus free electrons caused by the surface defect flow along an electric field in the depletion layers, and are accumulated in the photoelectric converter section 102 as dark electrons.
FIG. 11 shows the surface defect and a depletion layer DL as viewed from the cross-section of FIG. 9(a) along a B-B′ line. At an interface between the well 105 (an active region) and an element isolating region 111 (a non-active region), a surface defect SD is generated due to a stress at the time of forming the element isolating region 111, there are many free electrons at the interface. In the stationary state, since the surface defect SD is covered by the depletion layer DL generated at the portion of the surface of the well 105 under the gate electrode 106, free electrons caused by the surface defect SD flow along the electric field in the depletion layer DL, and are accumulated in the photoelectric converter section 102 as the dark electrons.
An accumulated amount of the dark electrons depends on a length of an exposure time, and thus in the case of shooting in a shooting mode for a long exposure time such as a shooting in a low-light environment, such problems will be caused as increases in the dark output and in variation in a dark signal among pixels, and deterioration in a white spot defect and the like. As is already applied to some of CCD solid-state imaging devices, an exemplary method for making the potential of the back gate region 113 almost 0V (pinning) by applying a negative voltage to the gate electrode 106 is suggested in order to solve the problem. Alternatively, a method for reducing an expansion of the depletion layer DL by increasing a threshold voltage Vth of the transistor 101 is suggested (see patent document 1).
Patent document 1: Japanese Laid-Open Patent Publication No. 11-274459